集成电路可测性设计（DFT）技术与实践培训发表时间：2024-03-01 09:10 使用人群：本科以上 培训大纲： 1、DFT overview DFT 概述 What is and Why DFT; VLSI implementation process; Manufacturing Defect; Manufacturing Test; Automatic Test Equipment (ATE) introduction 2、Test and fault 测试和故障 Observability and Controllability Role of Test Test Development Flow Real Tests DFT Cost Fault Modeling 3、DFT Methods introduction DFT 方法学介绍 DFT Methods Ad Hoc DFT Scan Basic Concept MBIST Basic Concept LBIST Basic Concept BSCAN Basic Concept JTAG Architecture IP Test 4、Mainstream DFT EDA tools and chip DFT integrated solutions.主流DFT 工具与芯片DFT技术介绍 DFT Compiler (DC); Mentor Testkompress/TessentMbist/ TessentBoundary Scan; Synopsys TetraMAX; Cadence Modus; DFT integrated solutions; 5、Scan introduction ( with DFT compiler)芯片scan技术介绍 Understanding Scan Testing; Scan Chain Insertion Flow Preview; Test Protocols and DRC; Test Ready Compile; Top Down Scan Insertion Flow; Bottom Up Scan Insertion Flow; Scan Compression method （XOR vs OPMISR）; Lab DFT Compiler introduce 6、ATPG introduction.芯片ATPG技术介绍 What is testing and ATPG Stuck at ATPG Transition ATPG Path delay ATPG IDDQ ATPG D algorithm 7、ATPG implementation ( with TestKompress/ TetraMAX Lab). 芯片ATPG技术实现 ATPG Flow Preview Building Design Design Rules Check Controlling ATPG Saving Pattern and Pattern Validation Lab TestKompress/TetraMAX introduce 8、Understanding MBIST 芯片MBIST技术介绍 Why Memory testing is required? Memory Faults Memory Testing Techniques Memory BIST algorithms Memory interface test (RAM Sequential Test) 9、MBIST Implement ( with Tessent MBIST Lab). 芯片MBIST技术实现 Tessent MBIST generation and insertion flow; ETChecker Introduction; Block Flow Planning with ETPlanner; ETAssemble and ETSignoff in the Block Flow; Memory BIST Hierarchical Top Level Flow; MBIST Diagnostics; Tessent MBIST parameters setting; Lab Tessent MBIST introduce; 10、DFT latest innovative technologies. 最新的DFT技术介绍 Channel Sharing of scan Cell aware ATPG technique ATPG Hierarchy scan technique Logic BIST/SCAN Hybrid technique Physical aware scan insertion 2.5D/3D Test IJTAG（IEEE 1687） Partial Good Test 11、DFT Flow and tools. 芯片项目中的DFT 流程和工具 DFT engineer 5 tasks DFT flow (top and block level) DFT flow inputs/outputs in each step DFT tools (flow used) 12、DFT SPEC and Checklist. 芯片项目中的DFT规格书和检查表 DFT spec of one chip DFT check-list in project DFT patterns check-list 13、Frequently see DFT problems (DFT architecture). 工程实践中的DFT常见问题（架构方案） Consider the three keys for DFT - Test costs/quality/yield; Define the whole chip DFT SPEC and test plan ; Implement Low-power scan inserting; Implement Low-power MBIST; Implement Low-power ATPG; 14、Frequently see DFT problems （Design and debug. 工程实践中的DFT常见问题（电路设计和调试） Tessent MBIST debug skills; Improve the scan test coverage; Insert test points; Insert On-Chip Clock Control; Deliver the DFT related SDC files for timing; DFT timing issue debug; Debug the mismatches in scan/mbist /bscan simulation 15、Frequently see DFT problems （ATE test）.工程实践中的DFT常见问题 （ATE测试） Troubleshooting Test Patterns ATE patterns fail - debug Scan diagnose flow Fault analysis Improve the yield 报名请点网站客服，询问更详细资讯 |
